SH7616 Datasheet, PDF (231/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
BAMRAL Bits 15 to 0—Break Address Mask A15 to A0 (BAMA15 to BAMA0): These bits
specify whether or not corresponding channel A break address bits 15 to 0 (BAA15 to BAA0) set
in BARAL are to be masked.
Bit 31 to 0:
BAMAn
Description
0
Channel A break address bit BAAn is included in break condition (Initial value)
1
Channel A break address bit BAAn is masked, and not included in condition
Note: n = 31 to 0
6.2.3 Break Bus Cycle Register A (BBRA)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
CPA1
0
R/W
6
CPA0
0
R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets four channel A
break conditions: (1) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (2) instruction
fetch/data access, (3) read/write, and (4) operand size. BBRA is initialized to H'0000 by a power-
on reset; after a manual reset, its value is undefined.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU/DMAC, E-DMAC Cycle Select A (CPA1, CPA0): These bits specify whether
a CPU cycle, or a DMAC or E-DMAC cycle, is to be selected as the bus cycle used as a channel A
break condition.
Bit 7:
CPA1
0
1
Bit 6:
CPA0
0
1
0
1
Description
Channel A user break interrupt is not generated
(Initial value)
CPU cycle is selected as user break condition
DMAC or E-DMAC cycle is selected as user break condition
CPU, DMAC, or E-DMAC cycle is selected as user break condition
Rev. 2.00 Mar 09, 2006 page 205 of 906
REJ09B0292-0200