SH7616 Datasheet, PDF (390/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
Write-Back Mode: When a cache hit occurs, the data is written to the data array of the matching
way according to the entry address, byte address in the line, and access data size, and the update
bit of that entry is set to 1. A write is performed only to the data array, not to external memory. A
write hit is completed in 2 cycles (figure 8.6).
Iφ
CPU pipeline
EX
MA
stage
EX
MA
EX
Cache
address bus
Address A
Address B
Address C
Cache tag comparison Cache tag comparison
Cache
data bus
Address A
Address B
EX: Instruction execution
MA: Memory access
Data array write
Figure 8.6 Write Access in Case of a Cache Hit (Write-Back)
When a cache miss occurs, the way for replacement is determined using the LRU information, and
the write address from the CPU is written in the address array for that way. Simultaneously, the
valid bit and update bit are set to 1. Since the 16 bytes of data for replacing the data array are
simultaneously read when the data on the cache bus is written to the cache, the address on the
cache address bus is output to the internal address bus and 4 longwords are read consecutively.
The access order is such that, for the address output to the internal address, the byte address within
the line is sequentially incremented by 4, so that the longword that contains the address to be read
from the cache comes last. The read data on the internal data bus is written sequentially to the
cache data array.
The internal address bus and internal data bus also function as pipelines, just like the cache bus
(figure 8.7).
Rev. 2.00 Mar 09, 2006 page 364 of 906
REJ09B0292-0200