SH7616 Datasheet, PDF (726/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in channel 0.
In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3: TGIED
0
1
Description
Interrupt requests (TGID) by TGFD bit disabled
Interrupt requests (TGID) by TGFD bit enabled
(Initial value)
Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2: TGIEC
0
1
Description
Interrupt requests (TGIC) by TGFC bit disabled
Interrupt requests (TGIC) by TGFC bit enabled
(Initial value)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1: TGIEB
0
1
Description
Interrupt requests (TGIB) by TGFB bit disabled
Interrupt requests (TGIB) by TGFB bit enabled
(Initial value)
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0: TGIEA
0
1
Description
Interrupt requests (TGIA) by TGFA bit disabled
Interrupt requests (TGIA) by TGFA bit enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 700 of 906
REJ09B0292-0200