SH7616 Datasheet, PDF (497/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit 3—Transfer Address Mode Bit (TA): Selects the DMA transfer address mode. The TA bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 3: TA
0
1
Description
Dual address mode
Single address mode
(Initial value)
Bit 2—Interrupt Enable Bit (IE): Determines whether or not to request a CPU interrupt at the end
of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is sent to the CPU when
the TE bit is set. The IE bit is initialized to 0 by a reset and in standby mode. Its value is retained
during a module standby.
Bit 2: IE
0
1
Description
Interrupt request disabled
Interrupt request enabled
(Initial value)
Bit 1—Transfer-End Flag Bit (TE): Indicates that the transfer has ended. When the value in the
DMA transfer count register (TCR) becomes 0, the DMA transfer ends normally and the TE bit is
set to 1. When TCR is not 0, the TE bit is not set if the transfer ends because of an NMI interrupt
or DMA address error, or because the DME bit in the DMA operation register (DMAOR) or the
DE bit was cleared. To clear the TE bit, read 1 from it and then write 0. When the TE bit is set,
setting the DE bit to 1 will not enable a transfer. The TE bit is initialized to 0 by a reset and in
standby mode. Its value is retained during a module standby.
Bit 1: TE
0
1
Description
DMA has not ended or was aborted
(Initial value)
Cleared by reading 1 from the TE bit and then writing 0
DMA has ended normally (by TCR = 0)
Rev. 2.00 Mar 09, 2006 page 471 of 906
REJ09B0292-0200