SH7616 Datasheet, PDF (600/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to
the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is
equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO
control register (SCFCR).
Bit 1: RDF
Description
0
The number of receive data bytes in SCFRDR is less than the receive trigger
set number
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When SCFRDR is read until the number of receive data bytes in SCFRDR
falls below the receive trigger set number, and 0 is written to RDF after
reading RDF = 1
• When SCFRDR is read by the on-chip DMAC until the number of receive
data bytes in SCFRDR falls below the receive trigger set number
1
The number of receive data bytes in SCFRDR is equal to or greater than the
receive trigger set number
[Setting condition]
When SCFRDR contains at least the receive trigger set number of receive data
bytes
Note:
SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number
of data bytes can be read. If all the data in SCFRDR is read and another read is performed,
the data value will be undefined. The number of receive data bytes in SCFRDR is indicated
by the lower 8 bits of SCFDR.
Rev. 2.00 Mar 09, 2006 page 574 of 906
REJ09B0292-0200