SH7616 Datasheet, PDF (8/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Item
Page
10.3.1 Descriptor 453
List and Data Buffers
Receive Descriptor 0
(TD0)
Revision (See Manual for Details)
Description amended
Bit 27—Receive Frame Error (RFE): Indicates that one or other bit of
the receive frame status indicated by bits 26 to 0 is set. Whether or
not the multicast address frame receive information which is part of
the frame status, is copied into this bit is specified by the
transmit/receive status copy enable register.
Bit 27: RFE
0
1
Description
No error during reception
(Initial value)
An error of some kind occurred during reception (see bits
26 to 0)
• Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0):
These bits indicate the error status during frame reception.
• RFS26 to RFS10—Reserved
• RFS9—Receive FIFO Overflow (corresponds to RFOF bit in
EESR)
• RFS8—Reserve Abort Detect
Note:
This bit is set to 1 when any of Receive Frame Status
bit 9, bit 7, bits 4 to 0 is set. When this bit is set, the
Receive Frame Error bit (bit 27: RFE) is set to 1.
• RFS7— Receive Multicast Address Frame (corresponds to
RMAF bit in EESR)
• RFS6—Reserved^*1
• RSF5— Receive Frame Discard Request Assertion
(corresponds to RFAR bit in EESR)^*1
• RFS4—Receive Residual-Bit Frame (corresponds to RRF bit in
EESR)
• RFS3—Receive Too-Long Frame (corresponds to RTLF bit in
EESR)
• RFS2—Receive Too-Short Frame (corresponds to RTSF bit in
EESR)
• RFS1—PHY-LSI Receive Error (corresponds to PRE bit in
EESR)
• RFS0—CRC Error on Received Frame (corresponds to CERF bit
in EESR)
Note: 1. Only HD6417616 is effective. HD6417615 is Reserved
bit.
Rev. 2.00 Mar 09, 2006 page viii of xxvi