SH7616 Datasheet, PDF (489/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
11.1.2 Block Diagram
Figure 11.1 shows the DMAC block diagram.
On-chip
memory
On-chip
peripheral
module
SARn
DARn
DREQn
Iteration
control
TCRn
On-chip peripheral
module request
BH
DACKn
DEIn
External
ROM
External
RAM
External I/O
(memory
mapped)
Register
control
Start-up
control
Request
priority
control
Interrupt
control
CHCRn
DMAOR
VCRDMAn
External I/O
(with
acknowledge)
Bus interface
Bus controller
DMAC
DMAOR: DMA operation register
SARn: DMA source address register
DARn: DMA destination address register
TCRn: DMA transfer count register
CHCRn: DMA channel control register
VCRDMAn: DMA vector number register
DEIn: DMA transfer end interrupt request to CPU
On-chip peripheral module request: Interrupt transfer request from on-chip SCIF, SIOF, SIO, TPU
BH: Burst hint
n: 0, 1
Figure 11.1 DMAC Block Diagram
Rev. 2.00 Mar 09, 2006 page 463 of 906
REJ09B0292-0200