SH7616 Datasheet, PDF (411/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
Bit 1—Magic Packet Detection Interrupt Permission (MPDIP): Controls interrupt notification by
the Magic Packet Detection bit.
Bit 1: MPDIP
0
1
Description
Interrupt notification by MPD bit in ECSR is disabled
Interrupt notification by MPD bit in ECSR is enabled
(Initial value)
Bit 0—Illegal Carrier Detection Interrupt Permission (ICDIP): Controls interrupt notification by
the Illegal Carrier Detection bit.
Bit 0: ICDIP
0
1
Description
Interrupt notification by ICD bit in ECSR is disabled
Interrupt notification by ICD bit in ECSR is enabled
(Initial value)
9.2.4 PHY Interface Register (PIR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
MDI MDO MMD MDC
Initial value: 0
0
0
0
*
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
Note: * Undefined
PIR provides a means of accessing PHY-LSI internal registers via the MII.
Bits 31 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3— MII Management Data-In (MDI): Indicates the level of the MDIO pin.
Bit 2— MII Management Data-Out (MDO): Outputs the value set to this bit by the MDIO pin
when the MMD bit is 1.
Bit 1— MII Management Mode (MMD): Specifies the data read/write direction with respect to the
MII. Read direction is indicated by 0, and write direction by 1.
Rev. 2.00 Mar 09, 2006 page 385 of 906
REJ09B0292-0200