SH7616 Datasheet, PDF (21/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

13.1.4 Register Configuration......................................................................................... 545
13.2 Register Descriptions ........................................................................................................ 545
13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 545
13.2.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 546
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 547
13.2.4 Notes on Register Access..................................................................................... 549
13.3 Operation........................................................................................................................... 550
13.3.1 Operation in Watchdog Timer Mode ................................................................... 550
13.3.2 Operation in Interval Timer Mode ....................................................................... 552
13.3.3 Operation when Standby Mode is Cleared........................................................... 552
13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 553
13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 553
13.4 Usage Notes ...................................................................................................................... 554
13.4.1 Contention between WTCNT Write and Increment............................................. 554
13.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 554
13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 554
13.4.4 System Reset with WDTOVF.............................................................................. 555
13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 555
Section 14 Serial Communication Interface with FIFO (SCIF)............................. 557
14.1 Overview........................................................................................................................... 557
14.1.1 Features ................................................................................................................ 557
14.1.2 Block Diagrams ................................................................................................... 559
14.1.3 Pin Configuration................................................................................................. 560
14.1.4 Register Configuration......................................................................................... 561
14.2 Register Descriptions ........................................................................................................ 562
14.2.1 Receive Shift Register (SCRSR).......................................................................... 562
14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 562
14.2.3 Transmit Shift Register (SCTSR) ........................................................................ 563
14.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 563
14.2.5 Serial Mode Register (SCSMR)........................................................................... 564
14.2.6 Serial Control Register (SCSCR)......................................................................... 567
14.2.7 Serial Status 1 Register (SC1SSR)....................................................................... 570
14.2.8 Serial Status 2 Register (SC2SSR)....................................................................... 575
14.2.9 Bit Rate Register (SCBRR).................................................................................. 578
14.2.10 FIFO Control Register (SCFCR) ......................................................................... 586
14.2.11 FIFO Data Count Register (SCFDR) ................................................................... 588
14.2.12 FIFO Error Register (SCFER) ............................................................................. 589
14.2.13 IrDA Mode Register (SCIMR)............................................................................. 589
14.3 Operation........................................................................................................................... 591
Rev. 2.00 Mar 09, 2006 page xxi of xxvi