SH7616 Datasheet, PDF (239/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
Break address mask register C (BAMRC) consists of two 16-bit readable/writable registers: break
address mask register CH (BAMRCH) and break address mask register CL (BAMRCL).
BAMRCH specifies which bits of the break address set in BARCH are to be masked, and
BAMRCL specifies which bits of the break address set in BARCL are to be masked. Operation
also depends on bits XYEC and XYSC in BBRC as shown below.
BAMRC Configuration
XYEC = 0
XYEC = 1
Address
X address
(when XYSC = 0)
Y address
(when XYSC = 1
Upper 16 Bits
(BAMC31 to BAMC16)
Upper 16 bits maskable
Maskable
—
Lower 16 Bits
(BAMC15 to BAMC0)
Lower 16 bits maskable
—
Maskable
Bit 31 to 0:
BAMCn
Description
0
Channel C break address bit BACn is included in break condition (Initial value)
1
Channel C break address bit BACn is masked, and not included in condition
Note: n = 31 to 0
Rev. 2.00 Mar 09, 2006 page 213 of 906
REJ09B0292-0200