SH7616 Datasheet, PDF (699/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

16.2.6 Serial Status Register (SISTR)
Bit: 15
14
...
4
—
—
...
—
Initial value: 0
0
...
0
R/W: R
R
...
R
Note: * Only 0 should be written, to clear the flag.
Section 16 Serial I/O (SIO)
3
TERR
0
R/(W)*
2
RERR
0
R/(W)*
1
TDRE
1
R/(W)*
0
RDRF
0
R/(W)*
SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to
H'0002 by a reset.
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit
underrun.
Bit 3: TERR
0
1
Description
Transmission is in progress, or has ended normally
(Initial value)
[Clearing conditions]
• When 0 is written to the TERR bit after reading TERR = 1
• When the processor enters the reset state
A transmit underrun error has occurred
TERR is set to 1 if data transmission is started while TDRE = 1
Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun.
Bit 2: RERR
0
1
Description
Reception is in progress, or has ended normally
[Clearing conditions]
• When 0 is written to the RERR bit after reading RERR = 1
• When the processor enters the reset state
A receive overrun error has occurred
RERR is set to 1 if data reception ends while RDRF = 1
(Initial value)
Rev. 2.00 Mar 09, 2006 page 673 of 906
REJ09B0292-0200