SH7616 Datasheet, PDF (474/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.3 Operation
The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data
between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC
itself reads control information, including buffer pointers called descriptors, relating to the buffers.
The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive
buffer in accordance with this control information. By setting up a number of consecutive
descriptors (a descriptor list), it is possible to execute transmission and reception continuously.
10.3.1 Descriptor List and Data Buffers
Before starting transmission/reception, the communication program creates transmit and receive
descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive
descriptor list start address registers.
Transmit Descriptor
Figure 10.2 shows the relationship between a transmit descriptor and the transmit buffer.
According to the specification in this descriptor, the relationship between the transmit frame and
transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer.
Notes: 1. The descriptor’s start address setting must be aligned with an address boundary that
corresponds with the descriptor’s length as set by the E-DMAC mode register
(EDMR).
2. The transmit buffer’s start address setting must be aligned with a longword boundary.
However, when SDRAM is connected, the setting must be aligned with a 16-byte
boundary.
Transmit descriptor
31 30 29 28 27 26
0
TD0
TFS26 to TFS0
31
TD1
TDL
16
31
0
TD2
TBA
Padding (4 bytes)
Transmit buffer
Valid transmit data
Figure 10.2 Relationship between Transmit Descriptor and Transmit Buffer
Rev. 2.00 Mar 09, 2006 page 448 of 906
REJ09B0292-0200