SH7616 Datasheet, PDF (154/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 4 Exception Handling
4.1.3 Exception Vector Table
Before exception handling begins, the exception vector table must be written in memory. The
exception vector table stores the start addresses of exception service routines. (The reset exception
table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. In exception handling, the start address of the
exception service routine is fetched from the exception vector table as indicated by the vector table
address.
Table 4.3 lists the vector numbers and vector table address offsets. Table 4.4 shows vector table
address calculations.
Table 4.3 (a)Exception Vector Table
Exception Source
Power-on reset
PC
SP
Manual reset
PC
SP
General illegal instruction
(Reserved by system)
Slot illegal instruction
(Reserved by system)
CPU address error
DMA address error (DMAC and
E-DMAC)
Interrupt
NMI
User break
H-UDI
(Reserved by system)
Trap instruction (user vector)
Vector
Number
0
1
2
3
4
5
6
7
8
9
10^*5
11
12
13
14
:
31
32
:
63
Vector Table Address
Offset
H'00000000–H'00000003
H'00000004–H'00000007
H'00000008–H'0000000B
H'0000000C–H'0000000F
H'00000010–H'00000013
H'00000014–H'00000017
H'00000018–H'0000001B
H'0000001C–H'0000001F
H'00000020–H'00000023
H'00000024–H'00000027
H'00000028–H'0000002B
H'0000002C–H'0000002F
H'00000030–H'00000033
H'00000034–H'00000037
H'00000038–H'0000003B
:
H'0000007C–H'0000007F
H'00000080–H'00000083
:
H'000000FC–H'000000FF
Vector Address
Vector number × 4
VBR + (vector
number × 4)
Rev. 2.00 Mar 09, 2006 page 128 of 906
REJ09B0292-0200