SH7616 Datasheet, PDF (405/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.1.4 Ethernet Controller Register Configuration
The Ethernet controller (EtherC) has the nineteen 32-bit registers shown in table 9.2.
Table 9.2 EtherC Registers
Name
Abbre-
viation R/W
EtherC mode register
EtherC status register
ECMR
ECSR
R/W
R/W^*1
EtherC interrupt permission register
ECSIPR R/W
PHY interface register
PIR
R/W
MAC address high register
MAHR
R/W
MAC address low register
MALR
R/W
Receive flame length register
RFLR
R/W
PHY status register
Transmit retry over counter register
Single Collision detect counter register
Delay Collision detect counter register
Lost carrier counter register
Carrier not detect counter register
Illegal frame length counter register
CRC error frame receive counter register
Frame receive error counter register
Too-short frame receive counter register
Too-long frame receive counter register
Residual-bit frame counter register
Multicast address frame counter register
PSR
TROCR
SCDCR
CDCR
LCCR
CNDCR
IFLCR
CEFCR
FRECR
TSFRCR
TLFRCR
RFCR
MAFCR
R
R/W^*2
R/W^*2
R/W^*2
R/W ^*2
R/W^*2
R/W^*2
R/W^*2
R/W^*2
R/W^*2
R/W^*2
R/W^*2
R/W^*2
Notes: All registers must be accessed as 32-bit units.
Reserved bits in a register should only be written with 0.
The value read from a reserved bit is not guaranteed.
1. Individual bits are cleared by writing 1.
2. Cleared by a write to the register.
Initial Value
H'00000000
H'00000000
H'00000000
H'0000000X
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
Address
H'FFFFFD60
H'FFFFFD64
H'FFFFFD68
H'FFFFFD6C
H'FFFFFD70
H'FFFFFD74
H'FFFFFD78
H'FFFFFD7C
H'FFFFFD80
H'FFFFFDB4
H'FFFFFD84
H'FFFFFD88
H'FFFFFD8C
H'FFFFFD90
H'FFFFFD94
H'FFFFFD98
H'FFFFFD9C
H'FFFFFDA0
H'FFFFFDA4
H'FFFFFDA8
Rev. 2.00 Mar 09, 2006 page 379 of 906
REJ09B0292-0200