SH7616 Datasheet, PDF (72/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.4 Source Register Data Formats for DSP Instructions
Register
Instruction
Guard Bits
39–32
A0, A1
DSP
operation
Fixed decimal, 40-bit data
PDMSB,
PSHA
Integer
24-bit data
Logic, PSHL, —
PMULS
Data
transfer
MOVX.W,
MOVY.W,
MOVS.W
MOVS.L
A0G, A1G
X0, X1, Y0,
Y1, M0, M1
Data
transfer
DSP
operation
MOVS.W
MOVS.L
Fixed decimal,
PDMSB,
PSHA
Data
Sign^*
Integer
Logic, PSHL, —
PMULS
Data
transfer
MOVS.W
MOVS.L
Note: * The sign is extended and stored in the ALU’s guard bits.
Register Bits
31–16
15–0
—
16-bit data
32-bit data
—
—
32-bit data
16-bit data
—
32-bit data
Rev. 2.00 Mar 09, 2006 page 46 of 906
REJ09B0292-0200