SH7616 Datasheet, PDF (673/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun.
Bit 2: RERR
0
1
Description
Reception is in progress, or has ended normally
(Initial value)
[Clearing conditions]
• When 0 is written to the RERR bit after reading RERR = 1
• When the RFRST bit in SIFCR is set to 1
• When the processor enters the reset state
A receive overrun error has occurred
RERR is set to 1 in the following cases:
• When the amount of primary receive data in SIRDR is 16 and the next
primary data receive operation completes
Bit 1—Transmit Data Register Empty (TDRE): Flag that indicates that primary data has been
transferred from SITDR to SITSR and the amount of data inside SITDR is less than or equal to the
setting of TFWM3 to TFWM0 in SIFCR.
Bit 1: TDRE
0
1
Description
Indicates that primary send data exceeding the transmit FIFO watermark
setting has been written to SITDR
TDRE is cleared to 0 in the following cases:
• When primary send data exceeding the setting of the transmit FIFO
watermark bits has been written to SITDR and 0 is written to TDRE after
reading TDRE = 1
• When the DMAC has written primary send data exceeding the setting of
the transmit FIFO watermark bits to SITDR
Indicates that the amount of primary send data in SITDR is less than or equal
to the transmit FIFO watermark setting
(Initial value)
TDRE is set to 1 in the following cases:
• When the amount of primary send data in SITDR is less than or equal to
the transmit FIFO watermark setting
• When the TFRST bit in SIFCR is set to 1
• When the processor is reset
Rev. 2.00 Mar 09, 2006 page 647 of 906
REJ09B0292-0200