SH7616 Datasheet, PDF (479/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 30—Receive Descriptor List Last (RDLE): Indicates that this descriptor is the last in the
receive descriptor list. After completion of the corresponding buffer transfer, the E-DMAC
references the first receive descriptor. This specification is used to set a ring configuration for the
receive descriptors.
Bit 30: RDLE
0
1
Description
This is not the last receive descriptor list
This is the last receive descriptor list (the next descriptor is inactive)
Bits 29 and 28—Receive Frame Position 1, 0 (RFP1, RFP0): These two bits specify the
relationship between the receive buffer and receive frame.
Bit 29:
RFP
0
1
Bit 28:
RFP
0
1
0
1
Description
Frame reception for receive buffer indicated by this descriptor continues
(frame is not concluded)
Receive buffer indicated by this descriptor contains end of frame (frame is
concluded)
Receive buffer indicated by this descriptor is start of frame (frame is not
concluded)
Contents of receive buffer indicated by this descriptor are equivalent to one
frame (one frame/one buffer)
Bit 27—Receive Frame Error (RFE): Indicates that one or other bit of the receive frame status
indicated by bits 26 to 0 is set. Whether or not the multicast address frame receive information
which is part of the frame status, is copied into this bit is specified by the transmit/receive status
copy enable register.
Bit 27: RFE
0
1
Description
No error during reception
(Initial value)
An error of some kind occurred during reception (see bits 26 to 0)
Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0): These bits indicate the error status
during frame reception.
• RFS26 to RFS10—Reserved
• RFS9—Receive FIFO Overflow (corresponds to RFOF bit in EESR)
• RFS8—Reserve Abort Detect
Rev. 2.00 Mar 09, 2006 page 453 of 906
REJ09B0292-0200