SH7616 Datasheet, PDF (542/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
11.4 Usage Examples
11.4.1 Example of DMA Data Transfer Between SCIF and External Memory
In this example data received by the serial communication interface with FIFO (SCIF) is sent to
external memory using DMAC channel 1. Table 11.10 lists the transfer conditions and register
setting values.
Table 11.10 Transfer Conditions and Register Setting Values for Data Transfer Between
On-chip SCIF and External Memory
Transfer Condition
Register Setting Value
Transfer source: SCFRDR1 in SCIF
SAR1
H'FFFFFCCC
Transfer destination: External memory (word space) DAR1
Transfer destination address
Number of transfers: 64
TCR1
H'0040
Transfer destination address: Increment
CHCR1 H'4045
Transfer source address: Fixed
Bus mode: Cycle-steal
Transfer unit: Byte
DEI interrupt request at end of transfer DE = 1
Channel priority: Fixed (0 > 1) DME = 1
DMAOR H'0001
Transfer request source (transfer request signal): SCIF DRCR1
(RXI)
H'05
Note: Make sure the SCIF settings have interrupts enabled and the appropriate CPU interrupt
level.
11.5 Usage Notes
1. DMA request/response selection control registers 0 and 1 (DRCR0 and DRCR1) should be
accessed in bytes. All other registers should be accessed in longword units.
2. Before rewriting the registers in the DMAC (CHCR0, CHCR1, DRCR0, DRCR1), first clear
the DE bit to 0 in the CHCR register for the specified channel, or clear the DME bit in
DMAOR to 0.
3. When the DMAC is not operating, the NMIF bit in DMAOR is set even when an NMI
interrupt is input.
4. The DMAC cannot access the cache memory.
Rev. 2.00 Mar 09, 2006 page 516 of 906
REJ09B0292-0200