SH7616 Datasheet, PDF (616/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit:
7
6
5
4
3
2
1
0
IRMOD PSEL RIVS
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R
R
R
R
R
Bit 7—IrDA Mode (IRMOD): Selects operation as an IrDA serial communication interface.
Bit 7: IRMOD
Description
0
Operation as SCIF is selected
1
Operation as IrDA is selected^*
(Initial value)
Note: * When operation as an IrDA interface is selected, bit 7 (C/A) of the serial mode register
(SCSMR) must be cleared to 0.
Bit 6—Output Pulse Width Select (PSEL): Selects either 3/16 of the bit length set by bits ICK3 to
ICK0 in the serial mode register (SCSMR), or 3/16 of the bit length corresponding to the selected
baud rate, as the IrDA output pulse width. The setting is shown together with bits 6 to 3 (ICK3 to
ICK0) of the serial mode register (SCSMR).
Serial Mode Register (SCSMR) SCIMR
Bit 6: Bit 5: Bit 4: Bit 3:
ICK3 ICK2 ICK1 ICK0
Bit 2:
PSEL Description
ICK3 ICK2 ICK1 ICK0
1
Pulse width: 3/16 of bit length set in bits ICK3 to
ICK0
Don’t Don’t Don’t Don’t
0
care care care care
Pulse width: 3/16 of bit length set in SCBRR
(Initial value)
Note: A fixed clock pulse signal, IRCLK, must be generated by multiplying the Pφ clock by 1/2 N +
2 (where N is determined by the value set in ICK3 to ICK0). For details, see section 14.3.6
Pulse Width Selection.
Bit 5—IrDA Receive Data Inverse (RIVS): Allows inversion of the receive data polarity to be
selected in IrDA communication.
Bit 5: RIVS
Description
0
Receive data polarity inverted in reception
(Initial value)
1
Receive data polarity not inverted in reception
Note: Make the selection according to the characteristics of the IrDA modulation/demodulation
module.
Bits 4 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 590 of 906
REJ09B0292-0200