SH7616 Datasheet, PDF (431/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
Illegal carrier
detection
Rx-DV negation
Idle
RE set
Reception
halted
RE reset
Reset
Start of frame
Preamble ^reception
detection
Wait for SFD
reception
SFD
reception
Promiscuous and other station
destination address
Destination
address
reception
Error
notification
Error
detection
Receive
error
detection
Own destination
address
or broadcast
or multicast
or promiscuous
Data
reception
Receive error
detection
End of
reception
Normal reception
CRC
reception
SFD: Start frame delimiter
Note: The error frame also transmits data to the buffer.
Figure 9.3 EtherC Receiver State Transitions
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
starts receive processing.
3. If the destination address matches the receiver’s own address, or if broadcast or multicast
transmission or promiscuous mode is specified, the receiver starts data reception.
4. Following data reception, the receiver carries out a CRC check. The result is indicated as a
status bit in the descriptor after the frame data has been written to memory.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.
Rev. 2.00 Mar 09, 2006 page 405 of 906
REJ09B0292-0200