SH7616 Datasheet, PDF (133/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 3 Oscillator Circuits and Operating Modes
Section 3 Oscillator Circuits and Operating Modes
3.1 Overview
Operation of the on-chip clock pulse generator, and CS0 area bus width specification, are
controlled by the operating mode pins. A crystal resonator or external clock can be selected as the
clock source.
3.2 On-Chip Clock Pulse Generator and Operating Modes
3.2.1 Clock Pulse Generator
A block diagram of the on-chip clock pulse generator circuit is shown in figure 3.1.
CAP1
CKIO
CAP2
EXTAL
XTAL
CKPREQ/CKM
MD2
MD1
MD0
CKPACK^*
PLL circuit 1
On/Off
Oscillator
PLL circuit 2
×1, ×2, ×4
DIVE
1/1
1/2
1/4
DIVM
1/1
1/2
1/4
DIVP
1/1
1/2
1/4
φ system clock
Eφ
External interface
clock
Iφ
CPU/DSP core
clock
Pφ
Peripheral module
clock
Clock mode control circuit
The relationship between the
internal clock frequencies is:
Iφ ≥ Eφ ≥ Pφ.
Maximum frequencies are:
Iφ, Eφ ≤ 62.5 MHz, Pφ ≤ 31.25 MHz.
Note: See section 21.4.4, Clock Pause Function.
Figure 3.1 Block Diagram of Clock Pulse Generator Circuit
Rev. 2.00 Mar 09, 2006 page 107 of 906
REJ09B0292-0200