SH7616 Datasheet, PDF (87/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the
pipeline, including modulo addressing, is indicated below.
if ( Operation is MOVX.W MOVY.W ) {
ABx=Ax; ABy=Ay;
/* memory access cycle uses ABx and ABy. The addresses to be used
have not been updated */
/* Ax is one of R4,5 */
if ( DMX==0 || DMX==1 && DMY==1 )} Ax=Ax+(+2 or R8[Ix} or +0);
/* Inc,Index,Not-Update */
else if (!not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,7 */
if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0; /* Inc,Index,Not-Update */
else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );
}
else if ( Operation is MOVS.W or MOVS.L ) {
if ( Addressing is Nop, Inc, Add-index-reg ) {
MAB=As;
/* memory access cycle uses MAB. The address to be used has not
been updated */
/* As is one of R2–5 */
As=As+(+2 or +4 or R8[Is] or +0); /* Inc.Index,Not-Update */
else { /* Decrement, Pre-update */
/* As is one of R2–5 */
As=As+(–2 or –4);
MAB=As;
/* memory access cycle uses MAB. The address to be used has been
updated */
}
/* The value to be added to the address register depends on addressing
operations.
For example, (+2 or R8[Ix] or +0) means that
+2:
if operation is increment
R8[Ix}:
if operation is add-index-reg
Rev. 2.00 Mar 09, 2006 page 61 of 906
REJ09B0292-0200