SH7616 Datasheet, PDF (274/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
3. When changing a register setting, the written value normally becomes effective in three cycles.
In an on-chip memory fetch, two instructions are fetched simultaneously. If the fetch of the
second instruction has been set as a break condition, even if the break condition is changed by
modifying the relevant UBC registers immediately after the fetch of the first instruction, a user
break interrupt will still be generated prior to the second instruction. To fix a timing at which
the setting is definitely changed, the last register value written should be read with a dummy
access. The changed setting will be valid from this point on.
4. If a user break interrupt is generated by an instruction fetch condition match, and the condition
is matched again in the UBC during execution of the exception service routine, exception
handling for that break will be executed when the interrupt request mask value in SR becomes
14 or below. Therefore, when masking addresses and setting an instruction fetch/post-
execution condition to perform step-execution, ensure that an address match does not occur
during execution of the UBC’s exception service routine.
5. Note the following when specifying an instruction in a repeat loop that includes a repeat
instruction as a break condition.
When an instruction in a repeat loop is specified as a break condition:
a. A break will not occur during execution of a repeat loop comprising no more than three
instructions.
b. When an execution-times break is set, an instruction fetch from memory will not occur
during execution of a repeat loop comprising no more than three instructions.
Consequently, the value in the break execution times register (BETRC or BETRD) will not
be decremented.
6. Do not execute a branch instruction immediately after reading a PC trace register (BRFR,
BRSR, or BRDR).
7. If CPU and DMAC bus cycles are set as break conditions when an execution-times break has
been set, BETR will only be decremented once even if CPU and DMAC condition matches
occur simultaneously.
8. UBC and H-UDI are used by the emulator. For this reason, the operation of UBC and H-UDI
may differ in some cases between the emulator and the actual device. If UBC and H-UDI are
not used on the user’s system, no register setting should be performed.
Rev. 2.00 Mar 09, 2006 page 248 of 906
REJ09B0292-0200