SH7616 Datasheet, PDF (671/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Bit 1—Enables data transmission. When this flag is cleared, the STXD pin goes to the high-
impedance state. When TM is set to 1, the STS pin also goes to the high-impedance state.
Bit 1: TE
0
1
Description
Transmission disabled: STxD pin goes to high-impedance state (Initial value)
When TM is set to 1, STS pin goes to high-impedance state
Transmission enabled
Bit 0—Receive Enable (RE): Enables data reception.
Bit 0: RE
0
1
Description
Reception disabled
Reception enabled
(Initial value)
15.2.6 Serial Status Register (SISTR)
Bit: 15 14 ... 9
8 ...
— — ... TCD RCD ...
Initial value: 0
R/W: R
0 ... 1
0 ...
R ... R/(W)^* R/(W)^* ...
Note: * Only 0 should be written, to clear the flag.
4
3
2
1
0
— TERR RERR TDRE RDRF
0
0
0
1
0
R R/(W)^* R/(W)^* R/(W)^* R/(W)^*
SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to
H'0002 by a reset. When the TFRST bit in SIFCR is set to 1, the TERR and TDRE bits are also
initialized. When the RFRST bit in SIFCR is set to 1, the RERR and RDRF bits are also
initialized.
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 645 of 906
REJ09B0292-0200