SH7616 Datasheet, PDF (191/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
Bits 14 to 8—Watchdog Timer (WDT) Interval Interrupt Vector Number 6 to 0 (WITV6–
WITV0): These bits set the vector number for the interval interrupt (ITI) of the watchdog timer
(WDT). There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Bus State Controller (BSC) Compare Match Interrupt Vector Number 6 to 0
(BCMV6–BCMV0): These bits set the vector number for the compare match interrupt (CMI) of
the bus state controller (BSC). There are seven bits, so the value can be set between 0 and 127.
5.3.7 Vector Number Setting Register A (VCRA)
Vector number setting register A (VCRA) is a 16-bit read/write register that sets the E-DMAC
interrupt vector numbers (0–127). VCRA is initialized to H'0000 by a reset. It is not initialized in
standby mode.
Bit: 15
—
Initial value: 0
R/W: R
14
EINV6
0
R/W
13
EINV5
0
R/W
12
EINV4
0
R/W
11
EINV3
0
R/W
10
EINV2
0
R/W
9
EINV1
0
R/W
8
EINV0
0
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 and 7 to 0—Reserved: These bits are always read as 0. The write value should always be
0.
Bits 14 to 8—Ethernet Controller Direct Memory Access Controller (E-DMAC) Interrupt Vector
Number 6 to 0 (EINV6–EINV0): These bits set the vector number for ethernet controller direct
memory access controller (E-DMAC) interrupt (EINT). There are seven bits, so the value can be
set between 0 and 127.
Rev. 2.00 Mar 09, 2006 page 165 of 906
REJ09B0292-0200