SH7616 Datasheet, PDF (6/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Item
Page Revision (See Manual for Details)
10.2.8
437 Description amended
Transmit/Receive
Status Copy Enable
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Register (TRSCER)
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
RMAFCE —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
Bits 31 to 8—Reserved These bits are always read as 0. The write value should always be 0.
Bit 7—Multicast Address Frame Receive (RMAF): Bit Copy Enable (RMAFCE)
Bit 7: RMAFCE
0
1
Description
Enables the RMAF bit status to be indicated in the RFS7 bit in the receive
descriptor.
Disables occurrence of corresponding source to be indicated in the RFS7 bit in
the receive descriptor.
10.3.1 Descriptor 450
List and Data Buffers
Transmit Descriptor 0
(TD0)
Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Description amended
Bit 27—Transmit Frame Error (TFE): Indicates that one or other bit of the transmit frame status
indicated by bits 26 to 0 is set.
Bit 27: TFE
0
1
Description
No error during transmission
An error of some kind occurred during transmission (see bits 26 to 0)
Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0): These bits indicate the error status
during frame transmission.
• TFS26 to TFS9—Reserved
• TFS8—Teransmit Abort Detect
Note: This bit is set to 1 when any of Transmit Frame Status bits 4 to 0 is set. When this bit is
set, the Transmit Frame Error bit (bit 27: TFE) is set to 1.
• TFS7 to TFS5—Reserved
Rev. 2.00 Mar 09, 2006 page vi of xxvi