SH7616 Datasheet, PDF (43/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 1 Overview
Type
Bus control
Symbol
CAS
OE
I/O
Output
Output
DQMUU/
WE3
DQMUL/
WE2
DQMLU/
WE1
DQMLL/
WE0
CAS3
Output
Output
Output
Output
Output
CAS2
Output
CAS1
Output
CAS0
Output
CKE
REFOUT
Output
Output
RD/WR
BUSHiZ
Output
Input
BH
Output
STATS0, 1 Output
Name
Function
Column
Synchronous DRAM CAS signal
address strobe
Output enable EDO DRAM output enable signal
Used in access in RAS down mode
Highest byte
access
SRAM/synchronous DRAM highest byte
select signal
Second byte
access
SRAM/synchronous DRAM second byte
select signal
Third byte
access
SRAM/synchronous DRAM third byte
select signal
Lowest byte
access
SRAM/synchronous DRAM lowest byte
select signal
Column address DRAM highest byte select signal
strobe 3
Column address DRAM second byte select signal
strobe 2
Column address DRAM third byte select signal
strobe 1
Column address DRAM lowest byte select signal
strobe 0
Clock enable
Synchronous DRAM clock enable signal
Refresh out
Signal requesting refresh execution
when the bus is released
Read/write
DRAM/synchronous DRAM write signal
Bus high
impedance
Signal used in combination with WAIT
signal to place bus and strobe signals in
the high-impedance state without the
ending bus cycle
Burst hint
Asserted at the start of a DMA burst,
negated one bus cycle before the end of
the burst
Status
CPU, DMAC, and E-DMAC status
information
Rev. 2.00 Mar 09, 2006 page 17 of 906
REJ09B0292-0200