SH7616 Datasheet, PDF (387/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

8.4 Cache Operation
Section 8 Cache
8.4.1 Cache Reads
This section describes cache operation when the cache is enabled and data is read from the CPU.
One of the 64 entries is selected by the entry address part of the address output from the CPU on
the cache address bus. The tag addresses of ways 0 through 3 are compared to the tag address parts
of the addresses output from the CPU. When there is a way for which the tag address matches, this
is called a cache hit (when any one of the way tag addresses and the tag address of the address
output from the CPU match). In proper use, the tag addresses of each way differ from each other,
and the tag address of only one way will match. When none of the way tag addresses match, it is
called a cache miss. Tag addresses of entries with valid bits of 0 will not match in any case.
When a cache hit occurs, data is read from the data array of the way that was matched according to
the entry address, the byte address within the line, and the access data size, and is sent to the CPU.
The address output on the cache address bus is calculated in the CPU’s instruction execution phase
and the results of the read are written during the CPU’s write-back stage. The cache address bus
and cache data bus both operate as pipelines in concert with the CPU’s pipeline structure. From
address comparison to data read requires 1 cycle; since the address and data operate as a pipeline,
consecutive reads can be performed at each cycle with no waits (figure 8.3).
Iφ
CPU pipeline stage
Cache address bus
Cache data bus
EX: Instruction execution
MA: Memory access
WB: Write-back
EX
MA
WB
EX
MA
EX
Address A Address B
Cache tag comparison
Address A Address B
Data array read
Figure 8.3 Read Access in Case of a Cache Hit
Rev. 2.00 Mar 09, 2006 page 361 of 906
REJ09B0292-0200