SH7616 Datasheet, PDF (461/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 9—Collision Detect Interrupt Permission (CDIP): Enables the collision detect interrupt.
Bit 9: CDIP
0
1
Description
Collision detect interrupt is disabled
Collision detect interrupt is enabled
(Initial value)
Bit 8—Transmit Retry Over Interrupt Permission (TROIP): Enables the transmit retry over
interrupt.
Bit 8: TROIP
0
1
Description
Transmit retry over interrupt is disabled
Transmit retry over interrupt is enabled
(Initial value)
Bit 7—Receive Multicast Address Frame Interrupt Permission (RMAFIP): Enables the receive
multicast address frame interrupt.
Bit 7: RMAFIP
0
1
Description
Receive multicast address frame interrupt is disabled
Receive multicast address frame interrupt is enabled
(Initial value)
Bits 6—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 5––Receive Frame Discard Request Assertion Interrupt Permission (RFARIP): Enables the
receive frame discard request assertion interrupt.
Bit 5: RFARIP
0
1
Description
Receive frame discard request assertion interrupt is disabled
Receive frame discard request assertion interrupt is enabled
(Initial value)
Bit 4—Receive Residual-Bit Frame Interrupt Permission (RRFIP): Enables the receive residual-bit
frame interrupt.
Bit 4: RRFIP
0
1
Description
Receive residual-bit frame interrupt is disabled
Receive residual-bit frame interrupt is enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 435 of 906
REJ09B0292-0200