SH7616 Datasheet, PDF (242/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
which bits of the break data set in BDRCL are to be masked. Operation also depends on bits
XYEC and XYSC in BBRC as shown below. BDMRCH and BDMRCL are initialized to H'0000
by a power-on reset; after a manual reset, their values are undefined.
BDMRC Configuration
XYEC = 0
XYEC = 1
Data
X data
(when XYSC = 0)
Y data
(when XYSC = 1)
Upper 16 Bits
(BDMC31 to BDMC16)
Upper 16 bits maskable
Maskable
—
Lower 16 Bits
(BDMC15 to BDMC0)
Lower 16 bits maskable
—
Maskable
Bit 31 to 0:
BDMCn
Description
0
Channel C break data bit BDCn is included in break condition (Initial value)
1
Channel C break data bit BDCn is masked, and not included in condition
Notes: 1. n = 31 to 0
2. When including the data bus value in the break condition, specify the operand size.
3. When specifying byte size, and using odd-address data as a break condition, set the
value in bits 7 to 0 of BDRC and BDMRC. When using even-address data as a break
condition, set the value in bits 15 to 8. The unused 8 bits of these registers have no
effect on the break condition.
Rev. 2.00 Mar 09, 2006 page 216 of 906
REJ09B0292-0200