SH7616 Datasheet, PDF (452/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.6 EtherC/E-DMAC Status Register (EESR)
EESR shows communication status information for both the E-DMAC and the EtherC. The
information in this register is reported in the form of interrupt sources. Individual bits are cleared
by writing 1 to them. Each bit can also be masked by means of the corresponding bit in the
EtherC/E-DMAC status interrupt permission register.
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
— RFCOF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 23
—
Initial value: 0
R/W: R
22
21
20
19
18
17
16
ECI
TC
TDE TFUF
FR
RDE RFOF
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
—
—
—
ITF
CND DLC
CD
TRO
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
RMAF
—
RFAR RRF RTLF RTSF PRE CERF
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Bits 31 to 25—Reserved: These bits are always read as 0. The write value should always read as 0.
Bit 24—Receive Frame Counter Overflow (RFCOF): Indicates that the receive FIFO frame
counter has overflowed.
Bit 24: RFCOF Description
0
Receive frame counter has not overflowed
(Initial value)
1
Receive frame counter overflow (interrupt source)
Note:
The receive FIFO in the E-DMAC can hold up to eight frames. If a ninth frame is received
when there are already eight frames in the receive FIFO, the receive frame counter
overflows and the ninth frame is discarded. Discarded frames are counted by the missed-
frame counter register. The eight frames in the receive FIFO are retained, and are
Rev. 2.00 Mar 09, 2006 page 426 of 906
REJ09B0292-0200