SH7616 Datasheet, PDF (378/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
peripheral module enables an access to the on-chip peripheral module without having to wait for
the completion of the write to low-speed memory.
During reads, the CPU always has to wait for the end of the operation. To immediately continue
processing after checking that the write to the device of actual data has ended, perform a dummy
read access to the same address consecutively to check that the write has ended.
The bus state controller’s write buffer functions in the same way during accesses from the DMAC.
A dual-address DMA transfer thus starts in the next read cycle without waiting for the end of the
write cycle. When both the source address and destination address of the DMA are external spaces
to the chip, however, it must wait until the completion of the previous write cycle before starting
the next read cycle.
The E-DMAC can perform access involving external memory, but not access involving any on-
chip memory or peripheral modules.
7.10.3 STATS1 and STATS0 Pins
The SH7616 has two pins, STATS1 and STATS0, to identify the bus master status. The signals
output from these pins show the external access status. Encoded output is provided for the
following categories: CPU (cache hit/cache disable), DMAC (external access only), E-DMAC,
and Others (refresh, internal access, etc..). All output is synchronized with the address signals.
The encoding patterns are shown in table 7.9, and the output timing in figure 7.59.
Table 7.9 Encoding Patterns
Identification
CPU
DMAC
E-DMAC
Others
STATS1
0
1
STATS0
0
1
0
1
Rev. 2.00 Mar 09, 2006 page 352 of 906
REJ09B0292-0200