SH7616 Datasheet, PDF (847/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 22 Electrical Characteristics
22.3.2 Control Signal Timing
Table 22.6 Control Signal Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
Symbol Min
Max
Unit Figure
RES rise and fall time
tRESr, tRESf —
200
ns
22.8
RES pulse width
tRESW
20
—
tPcyc
NMI reset setup time
tNMIRS
tPcyc + 10
—
ns
NMI reset hold time
tNMIRH
tPcyc + 10
—
ns
NMI rise and fall time
RES setup time^*
NMI setup time^*
IRL3–IRL0 setup time^*
tNMIr, tNMIf
tRESS
tNMIS
tIRLS
—
3tEcyc + 40
40
30
200
—
—
—
ns
ns
22.9
ns
ns
NMI hold time
IRL3–IRL0 hold time^*
tNMIH
20
tIRLH
20
—
ns
—
ns
BRLS setup time
tBLSS
10
—
ns
22.10
BRLS hold time
tBLSH
5
—
ns
BGR delay time
tBGRD
—
15
ns
Bus tri-state delay time
tBOFF
0
35
ns
Bus buffer on time
tBON
0
35
ns
Note: * The RES, NMI, and IRL3–IRL0 signals are asynchronous inputs. If the setup times shown
here are observed, a transition is judged to have occurred at the fall of the clock; if the
setup times cannot be observed, recognition may be delayed until the next fall of the clock.
t_RESf
t_RESr
RES
t_NMIr
t_NMIf
NMI
V_IH
V_IL
t_NMIRS
V_IH
V_IL
t_RESW
V_IH
V_IL
t_NMIRH
V_IH
V_IL
Figure 22.8 Reset Input Timing
Rev. 2.00 Mar 09, 2006 page 821 of 906
REJ09B0292-0200