SH7616 Datasheet, PDF (666/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
When transfer of control data to SIRSR is completed, the data contents are automatically
transferred to the receive control data register (SIRCDR), and the receive control data register full
flag (RCD) is set in SISTR.
If the next data word input operation ends before the RDRF flag is cleared, an overrun error
occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent
to the interrupt controller (INTC). The data in SIRSR overwrites the data in SIRDR.
If SIRCDR contains valid control data, SIRCDR is overwritten after the next control data input
operation completes.
15.2.2 Receive Data Register (SIRDR)
Bit: 15
14
13
...
3
2
1
0
...
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
SIRDR is a 16-bit x 16-stage FIFO register that stores primary receive data. When primary data is
transferred from SIRSR to SIRDR, the receive data register full flag (RDRF) is set in the serial
status register (SISTR), based on the settings of RFWM3 to RFWM0 in SIFCR. If the receive
interrupt enable flag (RIE) is set in SICTR, a receive-data-full interrupt (RDFI) request is sent to
the interrupt controller (INTC) and the DMA controller (DMAC). When the flag is cleared, this
interrupt request signal is not generated. When SIRDR is read by the DMAC, the RDRF flag is
cleared automatically if the value is less than or equal to the setting of bits RFWM3 to RFWM0 in
SIFCR. When SIRDR is reset, its status is empty. The status of SIRDR is also empty when the
value of the receive FIFO data registry reset bit (RFRST) in SIFCR is 1.
Note: Do not read from SIRDR when it contains no primary receive data (when the value of the
receive data register data count bits 4 to 0 (R4 to R0) in the FIFO data count register
(SIFDR) is 00000).
Rev. 2.00 Mar 09, 2006 page 640 of 906
REJ09B0292-0200