SH7616 Datasheet, PDF (629/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order or MSB-to-LSB order according
to the setting of the RLM bit in SC2SSR.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
a. Parity check: The SCIF checks whether the number of 1-bits in the receive data agrees with
the parity (even or odd) set in the O/E bit in the serial mode register (SCSMR).
b. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
c. Status check: The SCIF checks whether receive data can be transferred from the receive
shift register (SCRSR) to SCFRDR.
d. Break check: The SCIF checks that the BRK flag is 0, indicating no break.
If all the above checks are passed, the receive data is stored in SCFRDR. If a receive error is
detected in the error check, the operation is as shown in table 14.11.
Note: No further receive operations can be performed when an overrun error has occurred. The
setting of the EI bit in SC2SSR determines whether reception is continued or halted when
a framing error or parity error occurs.
Also, as the RDF flag is not set to 1 when receiving, the error flags must be cleared to 0.
4. If the RIE bit setting in SCSCR is 1 when the RDF or DR flag is set to 1, a receive-FIFO-data-
full interrupt (RXI) is requested.
If the RIE bit setting in SCSCR is 1 when the ORER, PER, or FER flag is set to 1, a receive-
error interrupt (ERI) is requested.
If the RIE bit setting in SCSCR is 1 when the BRK flag is set to 1, a break-receive interrupt
(BRI) is requested.
Rev. 2.00 Mar 09, 2006 page 603 of 906
REJ09B0292-0200