SH7616 Datasheet, PDF (584/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
 Synchronous mode
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
There is a single serial data communication format.
• Data length:
8 bits
• Receive error detection: Overrun errors
• IrDA 1.0 compliance
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. In addition, the transmitter and receiver both have a 16-stage
FIFO buffer structure, enabling continuous serial data transmission and reception.
(However, IrDA communication is carried out in half-duplex mode.)
• Built-in baud rate generator allows a choice of bit rates.
• Choice of transmit/receive clock source: internal clock from baud rate generator or external
clock from SCK pin
• Four interrupt sources
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently. The transmit-FIFO-data-empty and
receive-FIFO-data-full interrupts can activate the on-chip DMAC to execute data transfer.
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
• Choice of LSB-first or MSB-first mode
• In asynchronous mode, operation can be selected on a base clock of 4, 8, or 16 times the bit
rate.
• Built-in modem control functions (RTS and CTS)
Rev. 2.00 Mar 09, 2006 page 558 of 906
REJ09B0292-0200