SH7616 Datasheet, PDF (521/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.9 shows the combinations of request mode, bus mode, and address mode that can be
specified in the external request mode.
Table 11.9 Combinations of Request Mode, Bus Mode, and Address Mode Specifiable in
the External Request Mode
Dual Address Mode
Single Address Mode
Request Mode
Burst
Mode
Cycle-Steal
Mode
Burst
Mode
Cycle-Steal
Mode
External Level
Byte
request detection^*1 _Word
—
O
—
O
—
O
—
O
Longword
—
O
—
O
16-byte unit
—
—
—
—
Edge
Byte
detection^*2 _Word
O
O
O
O
O
O
O
O
Longword
O
O
O
O
16-byte unit
O
O
O
O
Notes: O: Can be set
—: Cannot be set
1. The same for high-level and low-level detection.
2. The same for rising-edge detection and falling-edge detection.
Bus Mode and Channel Priority: When a given channel (1) is transferring in burst mode and
there is a transfer request to a channel (0) with a higher priority, the transfer of the channel with
higher priority (0) will begin immediately. When channel 0 is also operating in the burst mode, the
channel 1 transfer will continue as soon as the channel 0 transfer has completely finished. When
channel 0 is in cycle-steal mode, channel 1 will begin operating again after channel 0 completes
the transfer of one transfer unit, but the bus will then switch between the two in the order channel
1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the
CPU. This example is illustrated in Figure 11.12.
Bus
state
CPU DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 CPU
ch0
ch1
ch0
ch1
ch0
CPU
DMAC ch1
Burst mode
DMAC ch1/ch0
bus right transfers
DMAC ch1
Burst mode
CPU
Figure 11.12 Bus Status when Multiple Channels are Operating
(when priority order is ch0 > ch1, ch1 is set to burst mode, and ch0 to cycle-steal mode)
Rev. 2.00 Mar 09, 2006 page 495 of 906
REJ09B0292-0200