SH7616 Datasheet, PDF (572/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.2.2 Watchdog Timer Control/Status Register (WTCSR)
Bit: 7
6
5
4
3
OVF WT/IT TME
—
—
Initial value: 0
0
0
1
1
R/W: R/(W)^* R/W
R/W
R
R
Note: * Only 0 can be written in bit 7, to clear the flag.
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register. The method of
writing to WTCSR differs from that of most other registers to prevent inadvertent rewriting. See
section 13.2.4, Notes on Register Access, for details. Its functions include selecting the timer
mode and clock source. Bits 7 to 5 are initialized to 000 by a reset, in standby mode, when the
clock frequency is changed, and in clock pause mode. Bits 2 to 0 are initialized to 000 by a reset,
but are not initialized in standby mode, when the clock frequency is changed, or in clock pause
mode.
Bit 7—Overflow Flag (OVF): Indicates that WTCNT has overflowed from H'FF to H'00 in
interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF
0
1
Description
No overflow of WTCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
WTCNT overflow in interval timer mode
(Initial value)
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. When WTCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
Description
Interval timer mode: interval timer interrupt (ITI) request to the CPU
when WTCNT overflows
(Initial value)
Watchdog timer mode: WDTOVF signal output externally when WTCNT
overflows. Section 13.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when WTCNT overflows in watchdog
timer mode
Rev. 2.00 Mar 09, 2006 page 546 of 906
REJ09B0292-0200