SH7616 Datasheet, PDF (334/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
after this is detected. Both banks will become inactive even in the bank active mode after the
refresh cycle ends or after the bus is released by bus arbitration.
CKIO
Tr
Tc
Td1
Td2
Td3
Td4
Tde
A24–A11
A10
A9–A1
CS3
RAS
CAS
RD/WR
DQMxx
D31–D0
DACKn*
Note: * DACKn waveform when active-low is specified.
Figure 7.27 (a) Burst Read Timing (No Precharge) Iφ : Eφ other than 1 : 1
Rev. 2.00 Mar 09, 2006 page 308 of 906
REJ09B0292-0200