SH7616 Datasheet, PDF (112/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Instruction
Instruction Code
Operation
STS MACH,Rn
STS MACL,Rn
0000nnnn00001010
0000nnnn00011010
MACH → Rn
MACL → Rn
STS PR,Rn
0000nnnn00101010 PR → Rn
STS DSR,Rn
STS A0,Rn
STS X0,Rn
STS X1,Rn
STS Y0,Rn
STS Y1,Rn
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
0000nnnn01101010
0000nnnn01111010
0000nnnn10001010
0000nnnn10011010
0000nnnn10101010
0000nnnn10111010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
DSR → Rn
A0 → Rn
X0 → Rn
X1 → Rn
Y0 → Rn
Y1 → Rn
Rn–4 → Rn, MACH → (Rn)
Rn–4 → Rn, MACL → (Rn)
Rn–4 → Rn, PR → (Rn)
STS.L DSR,@–Rn 0100nnnn01100010 Rn–4 → Rn, DSR → (Rn)
STS.L A0,@–Rn
0100nnnn01110010 Rn–4 → Rn, A0 → (Rn)
STS.L X0,@–Rn
0100nnnn10000010 Rn–4 → Rn, X0 → (Rn)
STS.L X1,@–Rn
0100nnnn10010010 Rn–4 → Rn, X1 → (Rn)
STS.L Y0,@–Rn
0100nnnn10100010 Rn–4 → Rn, Y0 → (Rn)
STS.L Y1,@–Rn
0100nnnn10110010 Rn–4 → Rn, Y1 → (Rn)
TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm ×
4 + VBR) → PC
Note: * The number of execution cycles before the chip enters sleep mode.
Cycles T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
8
—
Rev. 2.00 Mar 09, 2006 page 86 of 906
REJ09B0292-0200