SH7616 Datasheet, PDF (168/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 4 Exception Handling
4.8 Usage Notes
4.8.1 Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four, otherwise an address error will
occur when the stack is accessed during exception handling.
4.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four, otherwise an address error
will occur when the vector table is accessed during exception handling.
4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling
If the stack pointer value is not a multiple of four, an address error will occur during stacking of
the exception handling (interrupts, etc.). Address error exception handling will begin after the
original exception handling ends, but address errors will continue to occur. To ensure that address
error exception handling does not go into an endless loop, no address errors are accepted at that
point. This allows program control to be shifted to the address error exception service routine and
enables error handling to be carried out.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. In stacking of the status register (SR) and program counter (PC), the SP is decremented
by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The
address value output during stacking is the SP value, so the address where the error occurred is
itself output. This means that the write data stacked will be undefined.
4.8.4 Manual Reset during Register Access
Do not initiate a manual reset during access of a bus state controller (BSC), user break controller
(UBC), or pin function controller (PFC) register, or the frequency modification register (FMR),
otherwise a write error may result.
Rev. 2.00 Mar 09, 2006 page 142 of 906
REJ09B0292-0200