SH7616 Datasheet, PDF (267/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
If the break conditions for channels C and D are met at the same time, and the conditions had not
already been met for channel C, the conditions are considered to be met for channel C. Also, if the
conditions for channel C have already been met when the break conditions for channels C and D
are met at the same time, the conditions for channel D are considered to be met and a break
occurs.
However, if bus cycle conditions match for two of the channels included in the sequential
conditions, and if the bus cycle conditions (which is the first break condition for the adjacent
channel) have been specified as pre-execution break (PCB bit of BRCR set to 0) and (using the
break bus cycle register) instruction fetch, a break occurs and the BRCR condition match flag is
set to 1.
Bus X or bus Y may be selected in the sequential break setting, and it is also possible to set the
number of executions as a brake condition. For example, if an execution-times break is set for
channels C and D, a user break interrupt will be issued if, after the execution-times set for channel
set in BETRC has occurred, the execution-times condition set in BETRD for channel D is met.
6.3.7 PC Traces
1. A PC trace is started by setting the PC trace enable bit (PCTE) to 1 in BRCR. When a branch
(branch instruction, repeat, or interrupt) occurs the address that enables the branch source
address to be calculated and the branch destination address are stored in the branch source
register (BRSR) and branch destination register (BRDR). The address stored in BRDR is the
branch destination instruction fetch address. The address stored in BRSR is the last instruction
fetch address prior to the branch. A pointer indicating the relationship to the instruction
executed immediately before the branch is stored in the branch flag register (BRFR).
2. The address of the instruction executed immediately before the branch occurred can be
calculated from the address stored in BRSR and the pointer stored in BRFR. Designating the
address stored in BRSR as BSA, the pointer stored in BRFR as PID, and the address prior to
the branch as IA, then IA is found from the following equation:
IA = BSA – 2 × PID
Caution is necessary if an interrupt (branch) occurs before the instruction at the branch
destination is executed. In the case illustrated in figure 6.2., the address of instruction “Exec”,
executed immediately before the branch, is calculated from the equation IA = BSA – 2 × PID.
However, if branch “branch” is a delayed branch instruction with a delay slot and the branch
destination is a 4n+2 address, branch destination address “Dest” specified by the branch
instruction is stored directly in BRSR. In this case, therefore, equation IA = BSA – 2 × PID is
not applied, and PID is invalid. BSA is at a 4n+2 boundary in this case only, categorized as
shown in table 6.3.
Rev. 2.00 Mar 09, 2006 page 241 of 906
REJ09B0292-0200