SH7616 Datasheet, PDF (682/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Figure 15.4 shows interval transfer mode (SE set to 1 in SICTR) with LSB first (LM set to 1 in
SIFCR).
Figure 15.5 shows continuous transfer mode (SE cleared to 0 in SICTR) with LSB first (LM set to
1 in SIFCR).
Set to 1 when an amount of
data equal to or greater than the
setting of bits RFWM3 to RFWM0
in SIFCR is received
RDRF
Synchronous internal clock
SIRDR
A[7:0]
SIRSR
Undefined
A[0] A[0:1]
A[0:6]
A[0:7]
B[0]
SRCK
SRS
SRXD
A[0] A[1] A[2]
A[7]
Invalid
B[0] B[1]
Note: DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.4 Reception: Interval Transfer Mode/LSB First
Set to 1 when an amount of
data equal to or greater than the
setting of bits RFWM3 to RFWM0
in SIFCR is received
RDRF
Synchronous internal clock
SIRDR
A[7:0]
SIRSR
Undefined
A[0] A[0:1]
A[0:6] A[0:7] B[0] B[0:1] B[0:2]
SRCK
SRS
SRXD
A[0] A[1] A[2]
A[7] B[0] B[1] B[2] B[3]
Note: DL = 0: 8-bit data transfer
SE = 0: Asynchronous transfer, no start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.5 Reception: Continuous Transfer Mode/LSB First
Rev. 2.00 Mar 09, 2006 page 656 of 906
REJ09B0292-0200