SH7616 Datasheet, PDF (404/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.1.3 Pin Configuration
The EtherC has signal pins compatible with the 18-pin MII specified in the IEEE802.3u standard,
and three related signal pins to simplify connection to the PHY-LSI. The pin configuration are
shown in table 9.1.
Table 9.1 MII Pin Functions
Type
MII
Other
Abbre-
viation
TX–CLK
RX–CLK
TX–EN
ETXD0–
ETXD3
TX–ER
RX–DV
ERXD0–
ERXD3
RX–ER
CRS
COL
MDC
MDIO
LNKSTA
EXOUT
WOL
CAMSEN
Name
Transmit clock
I/O
Input
Receive clock
Input
Transmit enable
Output
Transmit data (4-bit) Output
Transmit error
Receive data valid
Output
Input
Receive data (4-bit) Input
Receive error
Input
Carrier detect
Collision detect
Management data
clock
Management data
input/output
Input
Input
Output
Input/
output
Link status
General-purpose
external output
Wake-On-LAN
CAM input
Input
Output
Output
Input
Function
TX-EN, ETXD0 to ETXD3, TX-ER timing
reference signal
RX-DV, ERXD0 to ERXD3, RX-ER timing
reference signal
Indicates that transmit data is ready on
ETXD0 to ETXD3
4-bit transmit data
Notifies PHY-LSI of error during transmission
Indicates that there is valid receive data on
ERXD0 to ERXD3
4-bit receive data
Identifies error state occurring during data
reception
Carrier detection signal
Collision detection signal
Reference clock signal for information
transfer via MDIO
Bidirectional signal for exchange of
management information between STA and
PHY
Inputs link status from PHY-LSI
External output pin
Magic packet reception
CAM match signal input function
Rev. 2.00 Mar 09, 2006 page 378 of 906
REJ09B0292-0200