SH7616 Datasheet, PDF (778/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI)
18.1.2 H-UDI Block Diagram
Figure 18.1 shows a block diagram of the H-UDI.
TCK
TMS
TRST
TAP
controller
Internal
bus controller
H-UDI
interrupt signal
TDI
Decoder
SDIR
SDSR
SDDRH
16
SDDRL
TDO
Mux
SDIDR
SDIR: Instruction register
SDSR: Status register
SDDRH: Data register H
SDDRL: Data register L
SDBPR: Bypass register
SDBSR: Boundary scan register
TCK: Test clock
TMS: Test mode select
TRST: Test reset
TDI: Test data input
TDO: Test data output
SDIDR: ID code register
Figure 18.1 H-UDI Block Diagram
Rev. 2.00 Mar 09, 2006 page 752 of 906
REJ09B0292-0200