SH7616 Datasheet, PDF (649/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.5 Use of Transmit/Receive FIFO Buffers
The SCIF has independent 16-stage FIFO buffers for transmission and reception. The
configuration of these buffers is shown in figure 14.23.
TxD
RxD
SCFTDR
1st stage
2nd stage
3rd stage
SCTSR
P
P/G
SCRSR
PF
SCFRDR
1st stage
2nd stage
3rd stage
Error
counter
SC1SSR
PER3–PER0
FER3–FER0
16th stage
16th stage
Data
counter
SCFDR
T3–T0
R3–R0
Transmit data writes
by CPU or DMAC
Receive data reads
by CPU or DMAC
SCFER
ED15–ED0
Figure 14.23 Transmit/Receive FIFO Configuration
Rev. 2.00 Mar 09, 2006 page 623 of 906
REJ09B0292-0200