SH7616 Datasheet, PDF (530/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
• Synchronous DRAM one-cycle write
When a one-cycle write is performed to synchronous DRAM, the DACKn signal is
synchronized with the rising edge of the clock. A request by the request signal is accepted
while the clock is high during DACKn output.
Transfer Width
Byte/Word/Longword
Transfer^*1
DREQn Detection
Method
Level Detection
Transfer bus mode
Cycle-steal mode^*2
DACKn output timing Write DACK
Transfer address mode Single mode
Bus cycle
Basic bus cycle
Notes: 1. Do not set a 16-byte unit; operation is not guaranteed if this setting is made.
2. Cycle-steal mode must be set when DREQ is level-detected.
Clock
Bus cycle
DREQn
(Active high)
DACKn
(Active high)
RAS
CPU
CPU
DMAC1
CPU DMAC2
CPU DMAC3 CPU
Blind zone
1st
acceptance
2nd
acceptance
DACK1
3rd
acceptance
DACK2
4th
....
acceptance
DACK3
CAS
RD/WR
WEn/DQMxx
Figure 11.28 (a) Synchronous DRAM One-Cycle Write Timing
Transfer Width
Byte/Word/Longword
Transfer
DREQn Detection
Method
Edge Detection^*
Transfer bus mode
Burst mode
DACKn output timing Write DACK
Transfer address mode Single mode
Bus cycle
Basic bus cycle
Note: * Edge detection must be set when burst mode is selected as the transfer bus mode.
Rev. 2.00 Mar 09, 2006 page 504 of 906
REJ09B0292-0200