SH7616 Datasheet, PDF (259/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.20 Branch Flag Registers (BRFR)
Bit: 15
14
13
12
11
10
9
8
SVF
PID2
PID1
PID0
—
—
—
—
Initial value:
0
Undefined Undefined Undefined
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
DVF
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
The branch flag registers (BRFR) comprise a set of four 16-bit read-only registers. The BRFR
registers contain flags indicating whether the actual branch addresses (in a branch instruction,
repeat, interrupt, etc.) have been saved in BRSR and BRDR, and a 3-bit pointer indicating the
number of cycles from fetch to execution of the last instruction executed. The BRFR registers
form a FIFO (first-in first-out) queue for PC trace use. The queue is shifted at each branch.
Bits SVF and DVF are initialized by a power-on reset, but bits PID2 to PID0 are not.
Bit 15—Source Verify Flag (SVF): Indicates whether the address and pointer that enable the
branch source address to be calculated have been stored in BRSR. This flag is set when the
instruction at the branch destination address is fetched, and reset when BRSR is read.
Bit 15: SVF
0
1
Description
BRSR value is invalid
BRSR value is valid
(Initial value)
Bits 14 to 12—PID2 to PID0: These bits comprise a pointer that indicates the instruction buffer
number of the instruction executed immediately before a branch occurred.
Bits 14 to 12:
PID2 to PID0
Odd
Even
Description
PID indicates instruction buffer number
PID+2 indicates instruction buffer number
(Initial value)
Bits 11 to 8, 6 to 0—Reserved: These bits are always read as 0. The write value should always be
0.
Rev. 2.00 Mar 09, 2006 page 233 of 906
REJ09B0292-0200