SH7616 Datasheet, PDF (416/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.9 Transmit Retry Over Counter Register (TROCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
TROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9
Initial value: 0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
TROC8
0
R/W
Bit:
Initial value:
R/W:
7
TROC7
0
R/W
6
TROC6
0
R/W
5
TROC5
0
R/W
4
TROC4
0
R/W
3
TROC3
0
R/W
2
TROC2
0
R/W
1
TROC1
0
R/W
0
TROC0
0
R/W
TROCR is a 16-bit counter that indicates the number of frames that were unable to be transmitted
in 16 retransmission attempts. When 16 transmission attempts have failed, TROCR is incremented
by 1. When the value in this register reaches H'FFFF (65,535), the count is halted. The counter
value is cleared to 0 by a write to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Transmit Retry Over Count 15 to 0 (TROC15 to TROC0): These bits indicate the
number of frames that were unable to be transmitted in 16 retransmission attempts.
Rev. 2.00 Mar 09, 2006 page 390 of 906
REJ09B0292-0200