SH7616 Datasheet, PDF (31/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Item
User break
controller (UBC),
4 channels
(A, B, C, D)
Section 1 Overview
Specifications
• Interrupt generation based on independent or sequential conditions for
channels A, B, C, D
 Three sequential setting patterns: A → B → C → D, B → C → D,
C→D
• Settable break conditions: Address, data (channels C and D only), bus
master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write,
operand cycle (byte/word/longword)
• User break interrupt generated on occurrence of break condition
• Processing can be stopped before or after instruction execution in
instruction fetch cycle
• Break with specification of number of executions (channels C and D only)
Settable number of executions: max. 2¹² – 1 (4095)
• PC trace function
Branch source/branch destination can be traced in branch instruction fetch
(max. 8 addresses (4 pairs))
Rev. 2.00 Mar 09, 2006 page 5 of 906
REJ09B0292-0200